rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7838 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 preliminary technical data octal, 13-bit voltage-output dac with parallel interface functional block diagram input latch a dac latch a AD7838 v out a dutgnd ab v out b v out c dutgnd cd ref ab ref cd ref ef ref gh v out d v out e dutgnd ef v out f d12 d0 cs wr a0Ca2 ldacab ldaccd ldacef ldacgh power on reset input latch b dac latch b dac b dac a input latch c dac latch c input latch d dac latch d input latch e dac latch e dac d dac latch f dac f dac c dac e v out g dutgnd gh v out h input latch g dac latch g input latch h dac latch h dac h dac g input latch f control logic clr v ss v dd gnd features eight 13-bit dacs in one package full 13-bit performance without adjustments buffered voltage outputs offset adjust for each dac pair 6 5 v supply operation unipolar or bipolar output swing to 6 4.5 v output settling to 1/2 lsb in 5 m s double buffered digital inputs microprocessor and ttl/cmos compatible asynchronous load facility using ldac inputs clear function to user-defined voltage power-on-reset, outputs power up at dutgnd 44-lead plcc package pin compatible with max547 applications process control automatic test equipment general purpose instrumentation digital offset and gain adjustment arbitrary function generators avionics equipment general description the AD7838 contains eight 13-bit, voltage-output digital-to- analog converters (dacs). the output voltages are provided through on-chip precision output amplifiers into which an exter- nal offset voltage can be inserted via the dutgnd pins. the AD7838 operates from a 5 v 5% supply. bipolar output voltages with up to 4.5 v voltage swing can be achieved with no external components. the AD7838 has four separate refer- ence inputs; each is connected to two dacs, providing different scale output voltages for every dac pair. the AD7838 features double-buffered interface logic with a 13- bit parallel data bus. each dac has an input latch and a dac latch. data in the dac latch sets the output voltage. the eight input latches are addressed with three address lines. data is loaded to the input latch with a single write instruction. an asynchronous ldac input transfers data from the input latch to the dac latch. the four ldac inputs each control two dacs, and all dac latches can be updated simultaneously by asserting all ldac pins. an asynchronous clear input resets the output of all eight dacs to the relevant dutgnd. asserting clr resets both the dac and the input latch to bipolar zero (1000 hex). on power-up, reset circuitry performs the same function as clr . all logic inputs are ttl/cmos compatible. the AD7838 is available in a 44-lead plcc package.
C2C rev. 0 AD7838Cspecifications preliminary technical data parameter b units test conditions/comments accuracy resolution 13 bits relative accuracy 2 lsb max typically 0.5 lsb differential nonlinearity 1 lsb max guaranteed monotonic over tempera ture bipolar zero-code error 20 lsb max typically 5 lsb gain error 8 lsb max typically 1 lsb v dd power supply rejection 2 0.0025 %/% max d gain/ d v dd v ss power supply rejection 2 0.0025 %/% max d gain/ d v ss load regulation 0.3 lsb typ r l = unloaded to 10 k w reference inputs 3, 4 input range dutgnd v min v dd v max input impedance 5 k w min output characteristics maximum output voltage v dd C 0.5 v max minimum output voltage v ss + 0.5 v min dynamic performance voltage output slew rate 3 v/ m s typ output settling time 5 m s typ settling to 0.5 lsb of full scale 5 digital feedthrough 5 nv-s typ digital crosstalk 5 nv-s typ digital inputs v inh , input high voltage 2.4 v min v inl , input low voltage 0.8 v max i inh , input current 1 m a max v in = 0 v or v dd c in , input capacitance 6 10 pf max power requirements v dd 5 v nom 5% for specified performance v ss C5 v nom 5% for specified performance i dd 44 ma max typically 14 ma i ss 40 ma max typically 11 ma notes 1 temperature range for b version: C40 c to +85 c. 2 psrr is tested by changing the respective supply voltage by 5%. 3 for best performance, refxx should be greater than dutgndxx by 2 v and less than v dd C 0.6 v. the device operates with reference inputs outside this range, but performance may degrade. 4 reference input resistance is code dependent. 5 typical settling time with 1000 pf capacitive load is 10 m s. 6 guaranteed by design, not production tested. specifications subject to change without notice. (v dd = +5 v; v ss = C5 v; dutgndxx = gnd = 0 v; r l =10 k v and c l = 50 pf to gnd, t a 1 = t min to t max , unless otherwise noted. typical values are at t a = +25 8 c.)
AD7838 C3C rev. 0 preliminary technical data timing specifications 1 parameter limit at t min, t max units description t 1 10 ns min address valid to wr setup time t 2 0 ns min address valid to wr hold time t 3 50 ns min cs pulse width t 4 50 ns min wr pulse width t 5 0 ns min cs to wr setup time t 6 0 ns min cs to wr hold time t 7 50 ns min data valid to wr setup time t 8 0 ns min data valid to wr hold time t 9 5 m s typ output settling time t 10 100 ns min clr pulse width t 11 50 ns min ldac pulse width notes 1 all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. timing applies for all grades of the part. 2 rise and fall times should be no longer than 50 ns. specifications subject to change without notice. (v dd = +5 v; v ss = C5 v; dutgnd = gnd = 0 v, refxx = 4.096 v) a0, a1, a2 cs wr data v out clr ldac t 1 t 2 t 5 t 6 t 3 t 4 t 7 t 8 t 9 t 10 t 11 figure 1. timing diagram
AD7838 C4C rev. 0 preliminary technical data warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7838 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2 (t a = +25 c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C6 v digital inputs to gnd . . . . . . . . . . . . . C0.3 v to v dd +0.3 v refxx . . . . . . . . . . . . . . . . . . . . dutgnd C 0.3 to v dd +0.3 dutgndxx . . . . . . . . . . . . . . . . . . . . . v ss C 0.3 to v dd +0.3 v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dd to v ss max current into refxx pin . . . . . . . . . . . . . . . . . . 10 ma max current into any other signal pin . . . . . . . . . . 50 ma operating temperature range industrial (b version) . . . . . . . . . . . . . . . . C40 c to +85 c ordering guide relative temperature accuracy dnl package package model range (lsbs) (lsbs) description option AD7838bp C40 c to +85 c 2 1 plastic leaded chip carrier (plcc) p-44a storage temperature range . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c plcc package, power dissipation . . . . . . . . . . . . . tbd mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 48 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latchup. pin configuration 9 10 11 12 13 7 8 16 17 14 15 18 19 20 21 22 23 24 25 26 27 28 2144 3 4 5 6424140 43 35 36 37 38 39 33 34 31 32 29 30 pin 1 identifier top view (not to scale) v out g v out h v dd ref_gh dutgnd_gh gnd ldac _gh AD7838 v out b v out a v dd ref_ab dutgnd_ab ldac _ab cs wr a2 a1 ldac _ef d0 d1 d2 ldac _cd a0 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 v out c v out d v out e v out f v ss v ss ref_cd ref_ef dutgnd_cd dutgnd_ef clr
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